2c341b481e
The overhead of reading the framer registers is significant and can result in latency bumps / data drops on heavily loaded systems. Instead of checking all spans every millisecond when they are in alarm we will instead only check every 100 ms. On one test system, dropped the % CPU time spent in hard interrupt context from 10% per TDM4XX when all four spans are in alarm to closer to 2%. Signed-off-by: Shaun Ruffell <sruffell@digium.com> Acked-by: Michael Spiceland <mspiceland@digium.com> Acked-by: Russ Meyerriecks <rmeyerriecks@digium.com> git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/trunk@10231 a0bf4364-ded3-4de4-8d8a-66a801d63aff